Shinpei Kato, President and CEO of TIER IV, has spearheaded the in-house development of an AI semiconductor (SoC) tailored for Level 4 autonomous driving. Behind this move lies a strategy to accelerate the global deployment of autonomous driving systems through energy-efficient, domestically produced AI chips and open-source technology.

Key Elements of the Project and the Full Architecture of AI Chip Logic Design

TIER IV, Inc. (represented by President and CEO Shinpei Kato), the company leading the development of the autonomous driving software “Autoware,” has joined the “Next-Generation Edge AI Semiconductor Research and Development Project” promoted by Japan’s Japan Science and Technology Agency (JST). Under this initiative, TIER IV has initiated the proprietary development of a software-defined System-on-Chip (SoC) designed for Level 4 autonomous driving. This project is carried out as part of the research topic “Use-case Driven Functional Differentiation Physical AI Chip Design,” led by Professor Yoshihiro Kawahara at the Graduate School of Engineering, The University of Tokyo. TIER IV is tasked with the logic design of the AI chip, aimed at significantly improving the efficiency of inference processing in End-to-End (E2E) autonomous driving AI. The following diagram illustrates the overall structure of the project and the concept of an open ecosystem.

The defining feature of this endeavor is the commitment to release the developed AI chip logic design IP and the full toolchain—including compilers—as open-source assets free of charge. By creating an open development ecosystem that can be reused and expanded as a shared platform by diverse global and domestic players without relying on specific semiconductor manufacturers or proprietary development environments, the project aims to dramatically accelerate the domestic production and widespread adoption of power-efficient, high-performance automotive AI semiconductors.

Architectural Optimization for Transformer Models and Ultra-Low Power Consumption

In automotive Electronic Control Units (ECUs) designed to achieve Level 4 full autonomy, vast amounts of spatial data gathered from sensor suites like cameras and LiDAR must be processed in real time. Conventional general-purpose computing architectures have faced severe challenges regarding massive power consumption and data transfer latency. TIER IV’s dedicated architecture adopts computing circuits and memory layouts specifically optimized for inference processing in large-scale “Transformer models,” which have become the mainstream in modern autonomous driving AI. Specifically, by placing and reusing data required for AI execution directly inside the chip, the architecture minimizes the frequency of access and data transfer to external memory, thereby reducing computing power consumption to the absolute minimum.

The target specification overview for this dedicated SoC includes:

• Target Applications: Flexible scalability ranging from several-watt edge embedded devices to multi-ten-watt automotive ECUs

• Processing Mechanism: Hardware accelerators optimized for matrix operations and Attention mechanisms in Transformer models

• System Integration: Maximizing overall execution speed and power-to-performance ratio across “Autoware”

This specialized architecture enables continuous, seamless execution of advanced perception and decision-making workloads while strictly satisfying the rigorous thermal and power constraints of automotive environments.

Design Philosophy Ensuring Flexibility and Safety for Evolving AI

Introduction of TOSA Intermediate Representation and Reliability via Formal Verification

Because autonomous driving AI algorithms evolve rapidly, locking the hardware into a fixed AI model structure carries the risk of swift architectural obsolescence as technology advances. To overcome this challenge, TIER IV incorporates “TOSA” (Tensor Operator Set Architecture), a standardized intermediate representation bridging AI models and hardware. AI models developed in major frameworks such as PyTorch are converted into TOSA’s standard format, through which code generation and optimization take place. This decouples the AI software layer from the underlying hardware, establishing a loosely coupled relationship.

Consequently, even as new generations of AI models emerge, maximum performance can be continuously extracted by merely updating software layers like compilers and runtime environments—without needing to redesign the chip’s logic from scratch. This realizes a software-defined SoC. Furthermore, formal verification—a mathematical verification technique—is integrated into the process starting from TOSA. By mathematically tracking and proving numerical errors or translation discrepancies introduced during model conversion and quantization, the internal transparency and correctness of the system are objectively guaranteed, establishing the high reliability essential for Level 4 operations. The following conceptual diagram illustrates the data flow from AI models through TOSA down to the chip.

Integrating E2E AI and Safety Guardrails via a Hybrid Architecture

End-to-End (E2E) AI, which has recently emerged as a dominant paradigm, processes everything from camera video input to vehicle control output within a single massive neural network. It has drawn immense attention for its ability to replicate smooth, natural driving behaviors akin to human drivers. However, because E2E AI operates across astronomical numbers of parameters, it suffers from the “black box problem”—where humans cannot logically prove or explain the exact causal chain behind a specific driving decision. This presents a formidable obstacle when securing operational permits from regulatory bodies or investigating liabilities after an accident.

To address this, TIER IV has adopted a hybrid architecture that merges cutting-edge E2E AI with deterministic, rule-based control:

• E2E AI Models (AV 2.0): Comprehend context to generate natural, flexible driving trajectories like a human driver

• Deterministic Rule-Based Systems (AV 1.0): Strictly enforce physical safety constraints, such as adhering to speed limits and making complete stops at red lights

• Safety Guardrail Mechanism: Instantly intervenes to execute forced braking or collision avoidance if the AI generates hallucinations or unsafe instructions

By implementing and evaluating this multi-layered defense structure directly on its custom SoC, TIER IV delivers a practical commercial solution that leverages the exceptional adaptability of E2E AI while remaining fully accountable and explainable to administrative authorities and insurance providers.

Industrial Transformation and the Future of Domestic AI Semiconductors

An Android-Style Open Ecosystem Challenging Tesla’s Vertical Integration

The global autonomous driving market is increasingly bifurcating into two major paradigms: a closed, vertically integrated model (Apple style) epitomized by Tesla, and an open, horizontally specialized model (Android style) spearheaded by TIER IV. Tesla internally designs and manufactures vehicles, inference chips, AI models, and training data centers, committing tens of billions of dollars annually in massive capital expenditures. However, a strategy where a single company bears such astronomical investment costs inherently carries immense capital risks, making it nearly impossible for other companies to join or leverage its ecosystem.

In contrast, TIER IV—which completed its listing on the Tokyo Stock Exchange Growth Market on July 22, 2026 (Ticker: 593A)—steadfastly maintains an open strategy anchored by the free release of its core OS, “Autoware.” By utilizing the company’s “Co-MLOps” (Cooperative Machine Learning Operations) platform, participating automakers and Tier 1 suppliers can securely pool driving data to collaboratively train massive AI models. Partnering with a powerful alliance including Renesas Electronics, Hitachi Astemo, Suzuki, Isuzu Motors, and NVIDIA, TIER IV shares and distributes the immense costs of AI infrastructure and chip design across the entire industry, establishing a global counterweight to market monopolization by giant tech monopolies.

Government Strategic Investment and Outlook/Challenges for Adoption

The Japanese government has pledged by cabinet decision to deploy 10,000 autonomous driving service vehicles nationwide by FY2030. Furthermore, the public-private investment roadmap published in July 2026 projects total public and private investments reaching 101.6 trillion yen in the AI and semiconductor sectors by FY2040. Within this allocation, 10.5 trillion yen is earmarked for Physical AI (powering autonomous driving and robotics) and 68.0 trillion yen for core semiconductors, aligning public support for this SoC development perfectly with Japan’s key national growth strategy. The following graphic depicts the roadmap for autonomous driving adoption in Japan.

The future focus lies in making a smooth transition from research and development to volume production and commercialization. While TIER IV currently carries operating losses due to heavy upfront R&D investments, its goal is to establish its proprietary SoC and toolchain as industry standards, shifting to a business model that earns stable license fees and platform royalties as mass-production vehicles roll out. As the company steadily builds safety track records and driving data through Level 4 pilot operations on restricted routes in local municipalities such as Komatsu and Shiojiri, scaling out into private passenger cars and the broader SDV market in the 2030s will be the decisive factor in securing Japan’s sovereignty in the autonomous driving industry.

Reference Pages

• [TIER IV, Inc. Press Release] https://tier4.co.jp/updates/press-release/20241017-02

• [The Autoware Foundation] https://github.com/autowarefoundation/autoware

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