NVIDIA has begun shipping Spectrum-6, its newest network switch utilizing Co-Packaged Optics (CPO), while Japanese telecommunications giant NTT (Nippon Telegraph and Telephone Corporation) announced the commercialization of its own photonics-electronics convergence switches within fiscal year 2026. As the primary bottleneck in AI infrastructure shifts from GPU supply to network bandwidth, establishing common industry test technologies has become the key to widespread adoption and ecosystem building.

Copper Wiring Reaches Physical Limits as CPO Switch Shipments Begin

As the GPU supply shortages that previously hindered AI infrastructure expansion begin to ease, the interconnect layer within data centers has emerged as the new bottleneck. For the 448G PAM4 signals now required by AI switches, the distance traditional copper cables can reliably transmit data has shrunk to approximately 25 centimeters (about 9.8 inches). This is a drastic reduction from the 2-meter reach possible during the 112G era, making it extremely difficult to maintain connections solely with copper wiring in large-scale AI clusters spanning multiple racks.

The technology expected to overcome this physical barrier is Co-Packaged Optics (CPO), which integrates optical engines directly into the same package as the switch’s Application-Specific Integrated Circuit (ASIC). At the OCP APAC Summit 2026 held in Taipei, NVIDIA confirmed that its latest CPO switch, the Spectrum-6, has entered the production and shipping phase. Because CPO performs signal conversion just millimeters away from the chip, it eliminates the need for digital signal processing retimers required by traditional pluggable modules, potentially reducing power consumption to as little as one-fifth of current levels. NVIDIA’s product launch marks a decisive step toward a structural shift where data center power is redirected from transmission overhead back into core computing. Please refer to the diagram below.

Networking Efficiency Determines AI Factory Computational Performance

The importance of networking in the data center has evolved beyond simple communication; it is now the primary factor determining the overall computational efficiency of an “AI Factory”. Data indicates that in current AI training clusters, Model FLOPS Utilization (MFU)—the ratio of actual processing performed compared to theoretical peak performance—remains as low as 38% to 43%. This means more than half of the available computing power is sitting idle due to network overhead and data delivery delays.

When converted into financial terms, a data center built with a 500 million USD investment effectively wastes approximately 280 million to 310 million USD in computational capacity due to these network latencies. As AI models evolve from simple prompt-response systems into “Agentic AI” that autonomously executes multi-step tasks, the load on interconnects is expected to increase further. Unless the network can maintain data delivery speeds, adding more expensive GPUs will not yield linear performance gains. Resolving these bottlenecks through CPO implementation has an economic impact equivalent to nearly doubling the effective processing power of a cluster without purchasing a single additional GPU.

Photonics-Electronics Convergence Strategies and Ecosystem Challenges for Semiconductor Giants

TSMC’s “COUPE” Platform and Horizontal Expansion of Back-end Supply Chains

With the advancement of photonics-electronics convergence, semiconductor manufacturers are shifting their strategic focus from traditional “front-end” wafer fabrication to “back-end” packaging and implementation. TSMC (Taiwan Semiconductor Manufacturing Company) has unveiled its Silicon Photonics platform technology called “COUPE” (Compact Universal Photonic Engine), providing a clear roadmap for transitioning from copper to optical interconnects. COUPE uses SoIC (System on Integrated Chips) stacking technology to place electrical dies directly on top of photonic dies. This creates an ultra-low impedance interface between dies, succeeding in reducing the electricity-to-light conversion path to the shortest physical distance possible.

Furthermore, TSMC is accelerating the construction of a mass-production supply chain for Panel Level Packaging (PLP) and is strengthening horizontal collaboration with major Outsourced Semiconductor Assembly and Test (OSAT) providers like the Taiwan-based ASE Group. To secure its position in the AI supply chain, ASE Group increased its capital expenditure to 8.5 billion USD (approximately 1.4 trillion JPY) and established an automated PLP production line for 310mm x 310mm panels. Consequently, AI chips are entering a phase where performance is no longer defined by a single die but by advanced packaging technologies that integrate photonics to scale systems to the 1-trillion transistor level.

The Absence of Common Test Standards and Simulation: A Major Adoption Barrier

While CPO switch shipments have begun, the industry faces a significant hurdle: the lack of “common test standards” required for a healthy multi-vendor environment. ASE Group, one of the world’s largest OSAT companies, has issued warnings that the simulation infrastructure and common test protocols necessary for CPO remain underdeveloped. Currently, NVIDIA’s CPO production relies on a manufacturing platform developed through years of deep, bilateral integration with TSMC. As a result, no platform yet exists that allows other companies to replicate these results using the same specifications.

Without standardized wafer-level test protocols or agreed-upon simulation methods, every participant in the supply chain—from foundries and OSATs to system integrators—must maintain their own unique verification processes. This not only drives up manufacturing costs but also slows down the “learning curve” for yield improvement. Organizations like the OCP (Open Compute Project) are working to define these frameworks, but until they are finalized, data center operators face a difficult choice: remain dependent on NVIDIA’s proprietary ecosystem or wait for a mature multi-vendor environment. Please refer to the diagram below.

Japanese Companies’ “Structural Path to Victory” and Guidelines for Long-term Network Upgrades

Commercialization of NTT’s “IOWN” PEC-2 and the Advantage of Replaceable Engines

Regarding the social implementation of photonics-electronics convergence, Japan’s NTT is taking a highly practical and realistic approach under its “IOWN” (Innovative Optical and Wireless Network) initiative. NTT plans to start the commercial provision of PEC-2 (Photonics-Electronics Convergence) generation switches, which handle board-to-board connections with light, within fiscal year 2026. A standout feature of this Japanese product is the use of a “socket-type” implementation for the optical engines, making them replaceable. While typical CPO designs solder the optical engine to the substrate—requiring the replacement of the entire switch if an engine fails—NTT’s method allows for the replacement of only the failed engine, significantly reducing maintenance costs in data center operations.

NTT is also advancing its mass-production capabilities through collaborations with established partners like Broadcom for switch ASICs and Taiwan’s Accton Technology for system manufacturing. This positioning aims to establish NTT not just as a research provider but as a viable candidate for large-scale data center procurement. Furthermore, Japanese corporations such as Sumitomo Electric Industries, Furukawa Electric, and Fujikura hold dominant global market shares in “essential components” like laser diodes, optical connectors, and fusion splicers. This represents a structural strength for Japan, controlling the most critical parts of the AI infrastructure.

An 18-Month Grace Period: Critical Choices for Data Center Buyers in Next-Generation Upgrades

For data center operators evaluating next-generation network upgrades, the remaining time before current pluggable optical modules reach their physical limits is estimated to be approximately 18 months. According to Andy Bechtolsheim, co-founder of Arista Networks, the 49.6T switch generation will represent the upper limit for pluggable density, and this turning point will arrive in about 18 months. While interim technologies like XPO (eXtra-dense Pluggable Optics) are emerging to provide high-density optical connections, the eventual transition to CPO is considered inevitable.

Looking ahead, if a network upgrade is planned for 24 months or further in the future, waiting for the establishment of open CPO standards led by firms like Lightmatter or the test standards mentioned by ASE Group becomes a realistic option. Conversely, hyperscalers requiring immediate upgrades will likely adopt vertically integrated proprietary ecosystems like NVIDIA’s to resolve interconnect bottlenecks early. The goal for these early adopters is to maximize Return on Investment (ROI) by improving MFU from the current 38–43% to an estimated 55–65%. The speed at which test technology is standardized will be the watershed moment determining whether the industry can avoid “vendor lock-in” and foster healthy market competition.

Reference Page

• 【NVIDIA Announces Spectrum-X Photonics, Co-Packaged Optics Network Switch, to Scale AI Factories to Millions of GPUs】https://blogs.nvidia.co.jp/blog/nvidia-spectrum-x-co-packaged-optics-networking-switches-ai-factories/

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