Huawei has accelerated its “Ascend 960” AI accelerator rollout by up to nine months while introducing a dual-track strategy tailored separately for training and inference. As Nvidia’s market share in China plunges due to U.S. export restrictions, Huawei is aggressively pushing to end reliance on American technology through massive R&D investments and robust ecosystem building.

A Nine-Month Acceleration and Dual-Track Strategy for Training and Inference

Chinese telecommunications giant Huawei has fundamentally restructured its rollout plans for the “Ascend 960” AI accelerator. Originally scheduled for release in the fourth quarter of 2027 as a unified chip for all workloads, the company has pivoted to a dual-track roadmap: the training-focused “Ascend 960DT” is now slated for the first quarter of 2027 (advanced by three quarters), while the inference-focused “Ascend 960PR” will launch in the third quarter of 2027 (advanced by one quarter), pulling ahead the overall schedule by up to nine months. This shift reflects a rapid evolution in the AI market, where workloads are transitioning from initial model training to enterprise inference operations. Beyond splitting compute silicon by application, Huawei is adopting a holistic architectural approach that integrates optical interconnects, memory, and storage into a unified system. Furthermore, the company has established an annual product update roadmap, planning to introduce the “Ascend 970” in 2028 and the “Ascend 980” in 2029. These targets are driven by Huawei’s proprietary “Tau Scaling Law” (τ-scaling rule), which aims to double compute capacity and memory bandwidth with each successive generation.

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The SuperPoD Concept Powered by Near-Packaged Optics (NPO)

The most notable aspect of Huawei’s technological innovation is its strategic shift away from single-chip peak performance toward system-wide scalability. The newly unveiled “Atlas 960E SuperPoD” (Ascend 960 SuperNode) houses up to 4,096 NPUs in a single node, delivering 8 EFLOPS of FP8 compute performance and up to 1 PB of HBM capacity. At the core of this breakthrough is Near-Packaged Optics (NPO) technology, which places optical engines adjacent to the compute silicon. By deploying 5,500 units of its proprietary “Hi-ONE” optical interconnect products, Huawei has eliminated the need for 48,000 traditional 800G optical transceivers. This architecture reduces system power consumption by over 550 kW and raises system availability to 99.8%. Additionally, Huawei’s “Peerium Computing Architecture” and “UnifiedBus” connect CPUs, NPUs, and storage under a single protocol. Simulations indicate that in a 100,000-card cluster, this design boosts Model FLOPs Utilization (MFU) by 2.75 times compared to traditional 8-NPU server configurations.

Market Shift in China and Nvidia’s Declining Foothold

Precipitous Drop in Nvidia’s Market Share Triggered by U.S. Restrictions

The competitive landscape of China’s AI semiconductor market has undergone a dramatic shift following consecutive tightening of U.S. export controls since October 2022, which restricted advanced AI chips like the A100 and H100 as well as modified export-compliant variants. Prior to these restrictions, Nvidia commanded approximately 95% of the Chinese market. However, according to market research firm IDC, domestic Chinese GPU and AI chip makers achieved a combined 41% market share in 2025, with Huawei accounting for 20%. Investment bank Bernstein projects that Nvidia’s market share in China will plummet to around 8% by the end of 2026, while Huawei’s share is expected to expand to nearly 50%. Nvidia CEO Jensen Huang effectively conceded this retreat during an investor event in October 2025, acknowledging that the company’s market share in China had effectively dropped from 95% to zero and that internal financial models now assume zero Chinese revenue. Paradoxically, Washington’s export controls designed to contain Chinese technology have instead accelerated domestic self-reliance and import substitution.

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Widespread Adoption by ByteDance and Alibaba Driven by CUDA Compatibility

The adoption of domestic AI chips by Chinese tech giants has entered full-scale commercial deployment. ByteDance, the operator of TikTok, and e-commerce leader Alibaba are planning large-scale orders for Huawei’s inference-optimized “Ascend 950PR” chips. Huawei plans to ship approximately 750,000 units of this chip in 2026, having initiated mass production in April 2026. A pivotal factor behind its adoption by major cloud providers is the evolution of Huawei’s software platform, “CANN Next.” Nvidia previously held an impenetrable moat in the AI market due to its proprietary “CUDA” programming environment, which serves as the global standard for AI development. However, CANN Next dramatically improves CUDA compatibility at a practical level, allowing developers to migrate existing software assets with minimal re-engineering. Furthermore, the Ascend platform became the first Chinese hardware stack to be directly integrated as a supported backend within the official open-source PyTorch framework, rapidly expanding its developer ecosystem.

Huawei’s Corporate Strategy and Long-Term Challenges

Record $17 Billion R&D Expenditure Squeezes Profit Margins

To achieve technological self-reliance amidst ongoing U.S. sanctions, Huawei continues to channel unprecedented capital into research and development. According to its financial results for the first half of 2026, Huawei’s revenue grew by 9.5% year-over-year to 467.8 billion yuan (approx. \$66 billion). However, net profit attributable to the parent company plummeted by roughly 37% to 23.4 billion yuan (approx. \$3.3 billion). The primary driver behind this margin contraction was a 25.2% surge in H1 R&D expenditure to 121.4 billion yuan (approx. \$17 billion), accounting for a record 25.9% of total revenue. Rising memory semiconductor prices and advance procurement costs across the supply chain also weighed on earnings. Nevertheless, despite short-term profitability pressures, Huawei prioritizes foundational research and capital investments to overcome manufacturing bottlenecks, including vertical stacking and “logic folding” techniques used in its “Kirin 2026” chips to increase circuit density without relying on EUV (Extreme Ultraviolet) lithography equipment.

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Physical Manufacturing Constraints and Supply Capacity Bottlenecks

Despite swift technological advancements, Huawei and the broader Chinese semiconductor industry face severe physical constraints. U.S. equipment export bans prevent Chinese foundries like SMIC from procuring advanced EUV lithography systems, effectively capping domestic manufacturing capabilities at around the 7nm process node. Relying on older DUV (Deep Ultraviolet) equipment with multi-patterning techniques substantially increases production costs and reduces wafer yields. Furthermore, shortages of High Bandwidth Memory (HBM) and advanced packaging capacity continue to restrict production scale. A senior Huawei executive publicly stated that domestic demand for AI chips far outstrips current production capacity, leaving the company with insufficient supply even for Chinese clients and no immediate capacity for global expansion. Ultimately, the long-term success of Huawei’s “SuperNode” strategy—compensating for single-chip performance gaps through system-level scaling—will depend on proving sustained operational stability and cost efficiency in real-world deployments.

References

• 【Huawei News Keynote】https://www.huawei.com/en/news/2026/9/hc-wang-keynote
• 【PyTorch Conference China 2026】https://pytorch.org/blog/pytorch-conference-china-2026-advancing-the-open-source-ai-stack/

【#Huawei #AIChips #Ascend960 #Nvidia #SemiconductorSelfSufficiency #NearPackagedOptics #CUDACompatibility #BusinessAndEconomy】